Technical Information
This document covers technical information regarding the device, that may be of interest to the advanced user or researcher that needs to understand how the device works at the low levels. The information in here is not required to be read in order to use the device in most circumstances. The quick start guide and user manuals should be the first place to look for help.
Calibration
The Qstim uses both DACs and ADCs to move between the analog and digital domains on the device. The DAC is responsible for converting a current value that is input by the user into a voltage value that is fed to an onboard voltage controlled current source (VCCS) that produces the current output to one of the four outputs on the device. The ADCs are responsible for turning the voltages produced by circuitry that measures channel voltage and current into integer values that can be handled and processed by the processor. In an ideal world where all the electrical components used perfectly match their specified values and the data converter is absolutely linear, the relationship between the data converters digital and analog value is simple and constant across all the devices that have been manufactured. In the real world, this relationship is more complex and varies from device to device. In order to compensate for these differences, the devices have had to incorporate a calibration system that allows each of them to be calibrated according its unique hardware characteristics.
Calibration System Overview
The calibration data is device specific, it depends on the culmination of errors in the electrical components present on the board. For this reason, this data is not built into the firmware, but is stored on an I2C EEPROM present on the device. This makes it easy for the user to re-calibrate the device themselves through the Shell interface Shell Manual. The use of an external EEPROM allows the firmware to stay consistent across all the devices in circulation and makes EEPROM failure a simpler and more cost effective issue to deal with. The EEPROM is completely managed by the processor on board the device, there is no need to use an external programmer to load calibration data, it is both written and read through the devices processor.
Calibration Paradigm
Calibration revolves around mapping a data converter value to a physical property that is being measured or produced either directly or indirectly by the data converter. If the relationship between the two is linear, then all that is required is a some offset and scale value (y = mx+b) to map between the two. If the relationship isn't linear then it can get more complicated. While a mathematical expression relating the two nicely might exist. The development/evaluation of that expression in a reasonable time, might not be possible on a microprocessor with limited performance. A popular calibration paradigm on microprocessors involves lookup tables (LUTs). A LUT stores the physical property value that should be measured/ produced by the data converter for every single input/output level of the data converter. The performance overhead is tiny for the processor to translate between the two values, but comes at the cost of memory consumption. A 12-bit data converter (the resolution of all the data converters used in the device), requires a LUT with 4096 entries to map each level. Due to the large number of data converters used in this device, LUTs could not be implemented. The paradigm chosen was a combination of both the LUT and linear offset and scale. A low density lookup table that maps regularly spaced points in the data converter/physical property relationship is used and linear interpolation is used between the points. Naturally the higher the point density, the more accurate the conversion. This density is controlled by the firmware and has been set to ensure that enough memory is present for other processes. A graphical representation of this paradigm can be seen below.
The red line represents the relationship between the data converter values and physical properties. The points of contact between the red and blue line represent the points stored in the LUT. Values between these LUT points are linearly interpolated from them. Naturally the least amount of error is present where the blue and red lines are coincident. However as the data converters and the circuits that follow in this device are mostly linear, very little error is present in values between two interpolation points. It is intentional that the points in the LUT have a regular interval on the axis that is being translated from. The reason for this is that there is less of a processing overhead in finding which interval a given value falls in than if the intervals were irregularly sized. This is important as the current to DAC value needs to be done fast to allow for current updates during a stimulation event. Additionally, due to the large amount of ADC data that needs to be translated, processing overhead needs to be small.
What does the EEPROM Store?
While it may seem logical that the answer to this question is simply the LUTs as described in the section above, this is not the case. Rather, the user can store a calibration point pair, which consists of either a DAC or ADC value and its corresponding physical property, either Voltage or Current. The user can choose to store as little or as many points as they will to a certain limit as defined by the firmware (at the time of writing this is 60 points per data converter). However, storing no or only one calibration point is useless, as storing no points results in every value mapping to zero and storing a single point results in every value mapping to the single point. In both cases the relationship would be flat. Two points and beyond becomes useful.
It is very likely that the number of calibration points may be lower than the number of entries that the LUT table requires and that the spacing between the pairs are not regular, making them not suitable for placement in the table. Some conversion process has to be performed to achieve this, and this will be discussed further on on this page. However there are benefits to storing arbitrary calibration point pairs:
- More intuitive from the user perspective (don't need to know what is happening behind)
- The user does not have to be aware of specific points they need to store
- They can control either value in the pair and and measure the other (one side of the pair may be easier to control than the other)
Note on Similar Points
The user is not restricted from storing any calibration pair they desire, this means the user can store pairs where:
- Both the data converter and electrical properties are identical to another pair
- The same data converter value paired with different electrical property values
- The same electrical property values paired with different data converter values
The device will handle all three cases without malfunctioning, in the event there are identical calibration pairs, the calibration relationship will look no different as if the identical points were not present. In the other two scenarios things get a bit more complicated since the treatment depends on whether the data converter value or the electrical property value is the independent variable. For DAC calibration points, the electrical property is the independent variable, since current values are mapped to DAC values (ie. every current value can only map to a single DAC value, but the same DAC value can map to multiple current values). For the ADCs the opposite is true, since the ADC value is mapped towards an electrical property. The firmware will only use the first calibration point to appear in EEPROM out of a set of points with equal independent variables.
| Pair 1 | Pair 2 | Pair 3 | Pair 4 | Pair 5 | Pair 6 | |
|---|---|---|---|---|---|---|
| Output Current | -3mA | -0mA | 0mA | 0.1mA | 3mA | 2mA |
| DAC Value | 0 | 2047 | 2100 | 2047 | 4095 | 3000 |
The pairs in green are used to perform the LUT table conversion, the pair in red is ignored as the DAC cannot be set to both 2047 and 2100 at the same time. The reason 2100 is ignored is simply because it was the first value in the EEPROM to be stored for 0mA. It is a first come first serve basis.
EEPROM to LUT Table Conversion
Every time the device starts, the calibration pairs on the EEPROM are processed to produce values for the LUT tables in memory. This also occurs when updating the calibration using the required shell commands. Essentially the points in the LUT table are filled with points interpolated between the calibration pairs stored in the EEPROM. While this may seem like an inefficient way to store the calibration data, since it is quite likely that there will be a lower number of calibration points stored in EEPROM than will be stored in the LUT table, using the LUT table to perform a translation is still faster than interpolating even between only a few calibration pairs in the way that they are stored in EEPROM.
Fast Translation Using LUT
The whole paradigm revolves around the fact that faster translations can occur between data converter and physical property values when using a regularly spaced LUT rather than an irregularly spaced one. The increased speed comes in finding the interval in which the input point falls not in the actual interpolation. When the intervals are evenly spaced, a simple arithmetic operation can be used to determine the correct interval, when the intervals are irregularly, a search needs to be performed, which depending on implementation can take significantly more time. Additionally the time taken is somewhat dependant on the size of the LUT when irregularly spaced.
Data Acquisition
The QStim device acquires both the current produced by the stimulator as well as the voltage produced at the output for all four on board channels.
ADC Specifications
The ADC peripheral has a maximum clock rate of 42MHz due to two levels of clock prescalers between the system clock and the peripheral (peripheral bus prescaler and ADC prescaler). The ADC prescaler has division levels of 2, 4, 6 and 8. Currently a division level of 4 is used for a 21MHz (temporary) clock frequency.
The ADC is an SAR ADC with sample hold circuitry. The total number of clock cycles required to complete an ADC conversion is the sum of the sampling time (exposure time of signal to the sample hold circuitry) and the conversion time (determined by bit depth of the ADC, in this case 12 Bit, therefore 12 clock cycles). the sampling time is configurable between 3 and 480 clock cycles long. A sufficiently long period of time needs to be selected to ensure capacitive elements storing the value are completely charged for accurate reading. Factors such as output impedance of signal being measured come into play when determining a sufficient cycle count. The lower the cycle count the faster the sample rate of the acquisition system. Currently the sampling time is 84 cycles (temporary). This results in a total cycle time of 96 cycles. At 21MHz, a total ADC conversion takes 4.6 microseconds. The ADC is responsible for reading 8 different signals (4 currents, 4 voltages). The ADC makes successive readings on all these signals. The QStim processor has in fact 3 ADC peripherals, all of which are used. One handles only the four current signals, therefore a sample is taken every 4.6 * 4 = 18.4 microseconds per channel or a sample rate of 54kHz. Each of the two remaining ADCs record 2 voltage channels each, therefore a sample is taken every 4.6 * 2 = 9.2 microseconds or a sample rate of 108kHz.
Note to Self (Remove once sorted) Target sampling time is 15 cycles or less at 42MHz ADC clock. This results in 0.64uS total conversion time. Or 1.28uS per voltage channel. 781kHz sampling rate, therefore with Nyquist 390.5kHz is limit. Radc not given in datasheet for 3.3v, only 6k for 1.8v I think. 6k would be too high alone for 3 cycle sampling time, so must be lower... At 15 cycles 2k output impedance of signal is okay if assuming 6k Racd, in reality signal can probably have higher impedance. At this stage I am planning to low impedance output of opamp against adc, either in form of antialiasing filter or buffer so that I don't have to worry about cycle time.